The present invention relates generally to a network system in which a plurality of data stations are connected to a common signal line, the common signal line providing a means for transferring a serial (bit-serial) data between each data station and more particularly to the network system in which the transmission and reception of such serial data between the mutually addressed data stations are controlled on the basis of a synchronous signal generated and outputted on the single-wire common signal line.
FIG. 1 shows a conventional network system.
In FIG. 1, a single common signal line 501 is provided for connecting a plurality of stations S.sub.1, S.sub.2, . . . , S.sub.N. A format of a signal communicating with each station S.sub.1, S.sub.2, S.sub.N is a string (bit serial) as shown in FIG. 2. Such a signal format is called SDLC (Synchronous Data Link Communication) developed by IBM corporation. In this signal format shown in FIG. 2, [Fo] and [Fc] have a bit pattern of "01111110" indicating the start and end of the data string. In FIG. 2, [A] comprises normally eight serial bits and indicates a destination address to which a transfer data [I] is sent. In FIG. 2, [C] comprises normally eight serial bits and indicates a kind of the data [I]. In addition, [FCS] is provided for detecting an error in the data [I] generated during the transmission of the data [I].
In the SDLC format, however, the destination address [A] is indespensable for synchronization of data transmission and reception the data needs to be transferred in a single signal line 501 as well as [Fo] and [Fc]. Therefore, there is a problem in that since more time is required for transmitting such information bits as [Fo], [Fc], and [A] in addition to the time for the data [I], transmission efficiency of data is accordingly reduced.
To cope with such a transmission efficiency problem, a two-wire type network system has been proposed in which data string signal and address signal are sent on their separately used signal lines. In this network system, a predetermined code string signal is sent to each station via an exclusive synchronous signal transmission line so that addressing (selection of two data stations mutually communicated) and synchronization are taken with the code string signal for each station. This is exemplified by Japanese Patent Examined Open No. Sho. 52-13,367 tilted to a system for transmitting multiplex signals published on Apr. 14, 1977.
The disclosed network system shown in FIG. 3 comprises a plurality of pair of transmission station 704 and reception station 705 are connected mutually via the synchronous signal transmission line 702 and data transmission line 703. Such a synchronous signal as shown in (c) of FIG. 4 is sent to each station from a synchronous signal generator 701 via the synchronous signal line 702.
In the synchronous signal generator 701, a clock signal having a constant signal .tau. as shown in (a) of FIG. 4 and an M-series code repeating such an order as "H", "H", "H" "L", "L", "H", and "L" for a constant period T as shown in FIG. (b) of 4 are generated. The synchronous signal generator 701, furthermore, modulates the generated M-series code in a pulsewidth modulation manner so that such the synchronous signal as shown in (c) of FIG. 4 is outputted to the synchronous signal line 701.
As shown in FIG. 3, the transmission station 704 comprises: (a) a receiving circuit 706 which receives and demodulates the synchronous signal into the clock signal and original series code signal as shown in (a) and (b) of FIG. 4; (b) three-stage shift registers 707, 708, and 709 which shift sequentially the demodulated code series signal in synchronization with the clock signal derived from the receiving circuit 706; (c) a logic circuit 710 which enables a gate 711 to open when a logic operation of each output signal level of these shift registers 707, 708, and 709 is carried out and a predetermined logic result is established.
FIG. 5 shows a relationship between the outputs D1, D2, and D3 of the shift registers (S.R.) 707, 708, and 709 and output logic status X of the logic circuit 710 for each clock signal generation.
As shown in FIG. 5, a combination pattern of "L" and "H" of the output signals of the shift registers 707, 708, and 709 appears seven kinds separately for a period T of the code series signal.
Hence, if one of the seven kinds of combination patterns in each transmission station 704 is a condition of establishment in the logic circuit 710 (for example, "H", "H", and "L" as shown in FIG. 5), the logic condition of the logic circuit 710 is established once for a period T of the code series signal so that the gate 711 is enabled to open. Consequently, one bit constituting the serial data is sent from an output circuit 712 to the data transmission line 703 during the period T.
On the other hand, the reception station 705 comprises the reception circuit 713, three-stage shift registers (S.R.) 714, 715, and 716 and logic circuit 717. The gate 718 is enabled to open only when the predetermined combination is established for one period T of the series code signal so that one bit constituting the serial data is fetched into a signal input circuit 719 from the data transmission line 703 via the gate 718.
In this way, any one of the transmission stations 704 can transmit data with any one of the reception stations 705 which has a logic circuit 717 having the same logic establishment condition as that of the logic circuit 710 via the line 703. In addition, the transmission station 704 can take different synchronization with the other transmission/reception stations having other logic establishment conditions so that data transfer is made without collision of data.
However, since the synchronous signal line 702 and serial data signal line 703 are exclusively used in the disclosed two-wire type network system, the number of signal lines and the number of repeater and connectors usually increase so that the construction of the network system becomes complex, large-sized, and requires large expenditure.